A MIS transistor is a transistor that has a three-layer structure of metal-insulating film-semiconductor and the surface conductivity of the semiconductor is controlled through the insulator by applying a voltage to the metal electrode. For example, a MOS transistor with silicon dioxide as the insulating film is included therein. In particular, a MOS field-effect transistor (MOSFET) is generally used for a semiconductor integrated circuit.
As a method of introducing an impurity into a semiconductor substrate, solid phase diffusion and plasma doping etc. are included. However, used most typically is the ion implantation described above. The merit of the ion implantation is that the impurity profile (concentration distribution) and impurity concentration can be formed with a good reproducibility. Therefore, the ion implantation is typically used in a process of introducing an impurity into a semiconductor substrate to form a well, a source/drain etc.
However, the ion implantation has a demerit that a damage region is generated due to the ion-implanting. A `damage region` means a region that includes interstitial silicon atoms caused by a silicon atom in the semiconductor substrate being dispersed from a crystal lattice position due to the ion-implanting and a vacancy generated at the crystal lattice. In most cases, such a damage region can be recovered by thermal treatment to be conducted thereafter in a semiconductor fabrication process. Namely, the reduction of yield caused by the damage region is not so big, and no electrical abnormal leakage caused by the damage region occurs.
Also, the ion implantation has another demerit in that interstitial silicon atoms dispersed from a crystal lattice position due to the ion-implanting promotes the abnormal diffusion of impurities, i.e., enhanced diffusion. `Enhanced diffusion` means a phenomenon that an impurity, such as boron, and a silicon atom dispersed are formed into a pair and the pair including the impurity diffuses faster than an ordinary diffusion in bulk. The enhanced diffusion is difficult to control and adversely affects the electrical characteristics of the MOSFET.
In a MOSFET used for a semiconductor integrated circuit, lowering the threshold voltage as well as suppressing the short-channel effect is needed to meet the requirements of high integration, fine structure, high speed and low voltage (low consumed power). However, the enhanced diffusion causes an inverse short-channel effect in that the threshold voltage becomes higher at the short channel region rather than the long channel region. Furthermore, it may cause a punch-through at the short channel region.
As described above, in conventional methods for fabricating a MOSFET, the enhanced diffusion of impurities at the channel region is a reason preventing enhanced performance of the MOSFET.
On the other hand, the present inventors have proposed a MIS transistor and a method for making the same wherein enhanced diffusion can be suppressed in conducting ion implantation as described in Japanese patent application laid-open No. 8-18047(1996).
In the method of Japanese patent application laid-open No. 8-18047(1996), boron is implanted through the gate electrode and gate oxide film into the channel region of the MOSFET. Therefore, boron is introduced into the gate oxide film. However, due to boron existing in the gate oxide film, the long-term reliability of the gate oxide film may be deteriorated.
Before explaining a method for making a MIS transistor in the preferred embodiments, the aforementioned conventional method for making MOSFET will be explained below.
FIGS. 1A to 2B are cross sectional views showing a method for making n-MOSFET. At first, as shown in FIG. 1A, a field oxide film 102 in the device separating region and a sacrifice oxide film 103 in the device region are formed by using LOCOS (local oxidation of silicon) etc. on a p-type semiconductor substrate 101. Then, as shown in FIG. 1B, by ion-implanting boron (B) to control a threshold voltage of n-MOSFET through the sacrifice oxide film 103 into the device region, a p.sup.- channel region 104A is formed. In a typical process of fabricating the MOSFET, an impurity is implanted at several separated steps on several kind of conditions to optimize the impurity profile of channel region to suppress the short-channel effect and punch-through effect other than the control of threshold voltage. The thermal treatment is then conducted to recover the damage of the boron implantation and to activate boron in a nitrogen atmosphere. Thus, the p.sup.- channel region 104A is changed into an activated p.sup.- channel region 104B. Further, the sacrifice oxide film 103 is removed by etching. Then, as shown in FIG. 1C, gate oxide film 105 and a gate electrode 106 are sequentially formed.
Then, as shown in FIG. 2A, by ion-implanting arsenic (As) self-aligned to the gate electrode 106, a source/drain n.sup.+ region 107A is formed. Finally, as shown in FIG. 2B, the thermal treatment is conducted to sufficiently electrically activate the source/drain n.sup.+ region 107A formed by the arsenic implantation. Thereby, an activated source/drain n.sup.+ region 107B is formed, thereby obtaining n-MOSFET.
The mechanism of reverse short-channel effect will be explained below. FIGS. 4A and 4B are cross sectional views showing two n-MOSFETs with different channel lengths. FIG. 4A shows a long-channel n-MOSFET. For example, in forming n.sup.+ diffusion region 111 by ion-implanting arsenic, interstitial silicon atoms generates, and thereby the enhanced diffusion of boron happens. In this case, the boron concentration around the n.sup.+ diffusion region 111 is reduced as shown in FIG. 4A (a region 112 in FIG. 4A). Boron moved by the enhanced diffusion is captured by a defect region in the n.sup.+ diffusion region 111 or accumulated at a source/drain end (a region 114 in FIG. 4A) on the surface of substrate and just under a gate electrode 113A.
On the other hand, FIG. 4B shows a short-channel n-MOSFET. Due to this short channel, the boron concentration at the channel region becomes relatively higher (a region 114 in FIG. 4B), therefore the reverse short-channel effect generates. Further, in such an n-MOSFET with short channel, the punch-through may occur since a region 112 of a very low boron concentration is formed just under the region 114 of a high boron concentration. Namely, due to the enhanced diffusion, suppressing the short-channel effect and lowering the threshold voltage becomes difficult to realize. Accordingly, how to suppress the enhanced diffusion is a key concern.
Next, the method for fabricating n-MOSFET disclosed in Japanese patent application laid-open No. 8-18047(1996) will be explained in FIGS. 5A to 6B. At first, field oxide film 102, gate oxide film 105 and a gate electrode 106 are formed on a p-type semiconductor substrate 101 as shown in FIG. 5A. Then, as shown in FIG. 5B, a source/drain n.sup.+ region 107A is formed by ion-implanting arsenic self-aligned to the gate electrode 106. At this time, the source/drain n.sup.+ region 107A is not activated. Then, as shown in FIG. 5C, thermal treatment is conducted at a high temperature, e.g., 900.degree. C. for 10 min. or 1000.degree. C. for 30 sec. in a nitrogen atmosphere. Interstitial silicon atoms that generate in implanting arsenic and cause the boron enhanced diffusion can be re-connected with a vacancy by this thermal treatment, thereby almost disappearing.
Then, as shown in FIG. 6A, boron atoms of 10.sup.12 to 10.sup.13 /cm.sup.2 are implanted through the gate electrode 106 into the semiconductor substrate 101 to form a p.sup.- channel region 104A. Finally, as shown in FIG. 6B, thermal treatment is conducted at a temperature of 800 to 900.degree. C. in a nitrogen atmosphere to form an activated p.sup.- channel region 104B.
Thus, interstitial silicon atoms generated by the arsenic implantation almost disappear by the step in FIG. 5C and interstitial silicon atoms generated by the boron implantation of 10.sup.12 to 10.sup.13 /cm.sup.2 are not so many. Therefore, a significant enhanced diffusion does not occur in the thermal treatment of 800 to 900.degree..